Terence Kelly at University of Massachusetts

Terence Kelly

  • 2.5Overall Quality
  • 2.0Helpfulness
  • 3.0Clarity
  • 1.0Easiness

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Date
Class
Rating
Comment
12/15/06

CE602

Average Quality

Easiness1

Helpfulness2

Clarity3

Rater Interest5

Grade ReceivedN/A

The Verilog / VHDL class starts off really slow and the professor does "story time" where he pretty much reads the book to you verbatim. The project has the potential to be really hard and the homeworks take a lot of time, so start early.

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