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Terence Kelly
Professor in the Engineering department
at University of Massachusetts, Lowell, MA
are you Terence Kelly?
Overall Quality
2.5
Average Grade
N/A
Hotness
Helpfulness
2.0
Clarity
3.0
Easiness
1.0
Helpfulness
0
Clarity
0
Easiness
0
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1 Student Ratings
Rating Class Comment
12/15/2006
average
2 Helpfulness
3 Clarity
1 Easiness
CE602 Taken for Credit:N/A Attendance: N/A Textbook Use: What textbook? Rater Interest: It's my life Grade Received: N/A

The Verilog / VHDL class starts off really slow and the professor does "story time" where he pretty much reads the book to you verbatim. The project has the potential to be really hard and the homeworks take a lot of time, so start early.

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